Test for defective open pins on devices
By utilizing Opens Testing in your test program we can check for opens and identify a Manufacturing defect that is not easily seen under visual inspection.
It makes use of a property of most digital ICs in use in the mid-1990s: the lead frame, a metal framework that includes the devices input, output and power pins and their extensions up to the point where the silicon die is attached. The size and shape of the lead frame is fairly stable from device to device and vendor to vendor.
The technique uses an external plate, suspended above the digital part, and separated from the lead frame by the plastic or ceramic material of the device housing. The lead frame and the external plate form a small capacitor that can be measured by stimulation with an ac source. Each pin (inputs, outputs and power) consists of a part of the lead frame, and so each can be detected as a separate capacitance.
The property that makes this technique interesting for in-circuit test shows up when a device pin is not properly soldered to its trace on the board. In this case, there is an additional capacitor in series with the TestJet capacitor. This additional capacitance exists because there is a tiny air gap between pin and trace. This is a very small capacitance, much smaller than the TestJet capacitor. The series combination of the TestJet capacitor and this additional pin capacitor is smaller than either capacitor. So, the TestJet technique seeks to measure the capacitance at each device pin, and identify each pin that is significantly smaller than an expected (computed) value. A threshold value can be set for each pin to discriminate between well- and poorly-soldered connections.